MyHDL is a Python framework for modeling and simulating FPGA RTL designs. MyHDL designs can be converted to VHDL and/or Verilog. Unlike Migen, there is no "mini-language". Everything is written in standard Python with the help of specific classes, functions and decorators provided by the framework.

MyHDL is very comfortable in concept modeling: In simulation, everything is possible or almost. For example, a FIFO can be simulated using a list and a counter. Of course, this is not convertible to VHDL or Verilog. Once the concept is validated, the design elements will be coded so that they are convertible.

The simulation data can be exported to a file in vcd format. This file can be read by a software, like GtkWave, to display the waveforms. Many Python libraries can help in the design development. Matplotlib can display curves derived from simulation data. When designing photography filters, PIL can read images to inject them into the design during simulation. Many other possibilities are available to the designer.

  • MyHDL : Official WEB site
  • Github : Source code on github
  • Discourse : Online support by the community